1. Technical Field
The present invention relates in general to enhanced performance in multiscalar processor systems and in particular to a method and system for enabling floating point exception operation in a multiscalar processor system. Still more particularly, the present invention relates to a method and system for enabling floating point exception operation in a multiscalar processor system without substantial performance degradation.
2. Description of the Related Art
Designers of modern state-of-the-art data processing systems are continually attempting to enhance the performance aspects of such systems. One technique for enhancing data processing system efficiency is the achievement of short cycle times and a low Cycle's-Per-Instruction (CPI) ratio. An excellent example of the application of these techniques to an enhanced data processing system is the International Business Machines Corporation RISC System/6000 (RS/6000) computer. The RS/6000 system is designed to perform well in numerically intensive engineering and scientific applications as well as in multi-user, commercial environments. The RS/6000 processor employs a multiscalar implementation, which means that multiple instructions are issued and executed simultaneously.
The simultaneous issuance and execution of multiple instructions requires independent functional units that can execute concurrently with a high instruction bandwidth. The RS/6000 system achieves this by utilizing separate branch, fixed point and floating point processing units which are pipelined in nature. In such systems a significant pipeline delay penalty may result from the execution of conditional branch instructions. Conditional branch instructions are instructions which dictate the taking of a specified conditional branch within a application in response to a selected outcome of the processing of one or more other instructions. Thus, by the time a conditional branch instruction propagates through a pipeline queue to an execution position within the queue, it will have been necessary to load instructions into the queue behind the conditional branch instruction prior to resolving the conditional branch in order to avoid run-time delays.
Another source of delays within multiscalar processor systems is the nonsynchronous nature of the operation of a floating point processor unit. Instruction addresses for instructions which are coupled to a floating point processor unit are lost and thus, in the event an instruction within a floating point processor unit cannot be executed, the exception caused by that failure to execute will stop the entire process. The Institute of Electrical and Electronics Engineers has promulgated a listing of a variety of exceptions which may occur within a floating point processor unit and how those exceptions should be handled. See IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std. 754-1985. Some of these exceptions include Overflow, Underflow, Inexact, Invalid Operation, Divide by Zero, and others. Each of these exceptions has an associated capability to permit a trap to be taken or to return to some specified default result.
Floating point processor unit hardware typically specifies the exceptions that can be generated and how those exceptions are to be handled by the hardware in conformance with the IEEE standard. In prior art multiscalar processor systems two methods are generally available to transfer program execution from the application to an appropriate trap handler upon the occurrence of an exception: software polling; and, hardware interrupt. Software polling has an advantage in performance. Software can select when to poll for a possible enabled exception. For example, if the Divide-by-Zero exception is the only trap-enabled exception, the compiler may place the polling branch and link on exception instruction after each floating-point divide instruction. This method may be utilized if the type of exception handling can be determined at the time a program is compiled.
Due to the difficulty of determining what kind of exception may be encountered during an application execution it may be necessary to implement precise hardware interrupt handling of an exception. This mode of operation is generally known as precise floating point exception enabled operation and is typically implemented by placing the entire processor into a mode of executing only one instruction at a time. Each instruction must complete before the next instruction will be dispatched, including fixed point instructions. This method allows traps to be enabled or disabled at run time and permits a precise address for the instruction which caused the exception to be identified. While this technique permits the exact identification of an instruction which initiates a floating point exception, it typically results in a performance degradation of five to ten times the nominal processor speed.
Thus, it should be apparent to those skilled in the art that it would be beneficial to have a method and system which permits floating point exception enabled operation within a multiscalar processor system without substantially degrading processor performance.